AMD EPYC Gen4 9654P CPU GENOA

Powering Modern Data Centers

4th Gen AMD EPYC™ 9004 GENOA
96 CPU Cores
192 Threads
Boost Up to 3.7GHz
TDP 360W
Cache L3 384MB

$USD $5,735.00
*RRP Pricing*
To View Channel Discounts Please Login

Introducing 4th Generation 9004 series AMD EPYC™ Processors, Code-Named “Genoa”

4th Gen EPYC™ processors are designed to deliver accelerated business results while lowering costs, power, and server footprint.

Start configuring your own 4th Gen AMD EPYC Server!

H6S -1U

H6S - 2U

WS1 Workstation PCIe5

“Zen 4” Core

AMD EPYC™ 9004 Series processors include up to 96 “Zen 4” microarchitecture-based cores, built on 5nm process technology. “Zen 4” enables leadership memory bandwidth and capacity with 12 DDR5 channels, as well as next-gen I/O with PCIe® 5.0 and memory expansion with CXL™.

The ‘Zen 4’ core integrated into 4th Gen AMD EPYC processors is the first and only x86 server CPU built with 5nm fabrication technology.

HYBRID MULTI-DIE ARCHITECTURE

The multi-die architecture has enabled significant improvements for each processor generation since the beginning.

Multiprocessor Server Design

The flexibility of the SERDES enables the Infinity Fabric interconnects to share the same physical infrastructure of chip’s PCIe I/O. In Figure 6, these are labeled as ‘G’ and ‘P’ links, each of which supports 16 lanes of PCIe Gen 5 connectivity. In a single-socket configuration, all Infinity Fabric links are dedicated to PCIe I/O, affording 128 lanes of Gen 5 bandwidth on AMD EPYC 9004 Series processors.

SINGLE-SOCKET SERVER CONFIGURATIONS

AMD EPYC processors with no ‘P’ suffix can be used in single-socket and 2-socket configurations. Processor part numbers with a ‘P’ suffix are optimized for single-socket servers by dedicating the ‘P’ links for PCIe I/O connections only.

2-SOCKET SERVER CONFIGURATIONS

In these configurations, three or four 16-lane ‘G’ links are used to connect to the second processor. For I/O-intensive server designs, three links can be used as Infinity Fabric interconnects and one additional link from each CPU can be dedicated to PCIe Gen 5 I/O, bringing the server I/O capacity to 160 lanes.